With the vertical scaling of gate stacks and implementation of pre-metalized gates and replacement gates in semiconductor devices, the ability to pattern a precision resistor in the gate pattern is becoming extremely difficult. A precision resistor can be moved into the diffusion substrate. However, building the resistor into the bulk substrate carries a large capacitive penalty.
A need therefore exists for methodology enabling the formation of a low capacitance precision resistor in the bulk substrate, and for the resulting device.